Banca de DEFESA: RODRIGO PEDROSO MENDES

Uma banca de DEFESA de MESTRADO foi cadastrada pelo programa.
DISCENTE: RODRIGO PEDROSO MENDES
DATA: 29/07/2024
HORA: 16:00
LOCAL: https://meet.google.com/xiy-dtuu-iug
TÍTULO: Integrated Digital Control for Inductive Buck Converters in Portable Battery-Powered Applications
PALAVRAS-CHAVES: DC-DC Converter, digital control, inductive, step-down, digital pulse width modulation, window analog to digital converter, buck.
PÁGINAS: 150
GRANDE ÁREA: Engenharias
ÁREA: Engenharia Elétrica
RESUMO: A digital control system for fixed-frequency buck converters within the domain of Power Management Integrated Circuits (PMIC) in portable battery-powered applications was studied. It was assumed that the converter can be powered either by a Lithium-Ion battery (2.7 V to 4.2 V) or, during the charging of the battery, via a Universal Serial Bus (USB) port (4.7 V to 5.5 V). The load current may vary from 0 to 200 mA, the switching frequency is 2 MHz, and the output voltage aligns with the operational range of the native transistors available in the Complementary Metal-Oxide-Semiconductor (CMOS) 180 nm technology (assumed to be within 1.62 V to 1.98 V). The target accuracy of the output voltage was set to ±2% of the voltage reference in order to cope with possible variations of the voltage reference (which was not addressed in this study) while still maintaining the output voltage within the limits of commercial analog PMICs, like the nPM1300 from Nordic Semiconductor (±5% of the target). In order to obtain this accuracy, the proposed Digital Pulse Width Modulation (DPWM) integrates an input voltage feed-forward scheme, resulting in an output voltage variation of less than 6 mV under line transients. The Analog-to-Digital Converter (ADC) was designed with a typical step size of 2.136 mV, a quiescent current of 15.5 µA, and an estimated area of 0.0088 mm2. The work on the ADC and DPWM was carried out at the schematic level only, with significant effort dedicated to validating these sub-blocks under variations in process, mismatch, supply voltage, and temperature. A synthesizable Verilog model for the digitally controlled logic was proposed and validated in the system level through Verilog-AMS simulations with the schematics of the ADC and DPWM.
MEMBROS DA BANCA:
Presidente - 1725390 - ANTONIO AUGUSTO LISBOA DE SOUZA
Interno - 2333186 - CICERO DA ROCHA SOUTO
Interno - 1558977 - DARLAN ALEXANDRIA FERNANDES
Externo à Instituição - FERNANDO RANGEL DE SOUSA